ClearNAND

clearNAND

Paving the Way for Advanced NAND Solutions

ClearNAND™ Flash is like regular NAND—the interface and package types are the same—but ClearNAND integrates a controller and NAND die in an MCP. It manages the required ECC, enables easy migration, and, in the case of Enhanced ClearNAND Flash, also offers several performance-enabling features for enterprise applications.

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ClearNAND Flash is Micron’s response to the industry’s demands for a higher capacity solution that also addresses existing and future ECC concerns. While we’ve been aggressively shrinking our technology processes to meet those demands, we also recognize that process shrinks have a direct effect on NAND performance and endurance and make error correction increasingly difficult to manage.

By applying our intellectual property and memory design expertise to this challenge, we were able to develop ClearNAND Flash. ClearNAND technology is an integrated solution that not only improves performance; it also extends the life of raw NAND by enabling future process generations to be easily adopted and designed in to enterprise, consumer, and computing applications.

ClearNAND Part Catalog and Documentation



ClearNAND Family
ClearNAND devices are like regular NAND—the interface and package types are the same—but they integrate a controller into that package, along with up to eight NAND devices. The internal controller offloads ECC from the host controller, freeing designers from having to adjust their design every time the NAND changes. Micron is offering two versions of the ClearNAND family: standard and enhanced.

Standard ClearNAND: ONFI-Compatible, Drop-In Replacement
Standard ClearNAND Flash is a drop-in replacement for consumer applications where ECC complexities need to be managed. It’s manufactured on our 25nm NAND technology, implements the required ECC, and provides a traditional asynchronous ONFI bus (following the ONFI EZ NAND protocol) for ease of migrating from standard NAND to ClearNAND Flash.

Enhanced ClearNAND: Enterprise-Class Features
Enhanced ClearNAND Flash provides increased speed and high endurance for enterprise applications, along with several key features that enable better, more efficient designs. It supports both the asynchronous and synchronous versions of the ONFI 2.2 interface.

Enhanced ClearNAND Advanced Features
Interface Simplification
ClearNAND Flash enables 8X higher density with fewer pins than raw NAND. Using fewer pins saves power and reduces package size, which can reduce costs.

DQ Mirroring
The ClearNAND controller recognizes whether it's been placed as a back side package and reorders the DQ pins to simplify PCB traces and simplifies inventory management compared with having separate packaging types.

Intelligent Interrupt
Raw NAND uses a simple R/B signal, which is acceptable for designs with only a few NAND but quickly becomes unusable for larger implementations. Designers have been forced to use "enhanced status" commands to continually ping each die to determine whether it’s ready for a command. This eats power and processing cycles. ClearNAND Flash simplifies this by redefining ready/busy pins into a single interrupt pin, providing better speed, and reducing power consumption. ClearNAND "watches" the status of each die and when an individual die is ready for the next operation, the interrupt pin informs the external controller of this, saving power and processing.

Internal Copyback
During wear leveling, raw NAND occupies an ONFI channel to copy data to the controller, error correct it, and copy it back to the target die. ClearNAND Flash can perform this function internally, keeping the channel free. The command still has to be issued from the controller, but it takes nanoseconds compared to microseconds. This opens the door to incredible performance possibilities.

Features   Benefits
Density 8-16GB (Standard)

32-64GB (Enhanced)		 Industry-leading densities
Interface Speed 50 MT/s (Standard)

200 MT/s (Enhanced)		 Increased speeds improve user-perceptible performance
Interface ONFI 2.3 Async (Standard)

ONFI EZNAND 2.3 Async/Sync plus*
(Enhanced)
 Standard interface enables a high degree of interoperability and backward compatibility. *ClearNAND Enhanced parts provide an extended command set.
Endurance 3k cycles (Standard)

 5k cycles (Enhanced)		 High endurance enables applications that need intensive PROGRAM/ERASE operations and prolongs memory life
Package 52-ball LGA (Standard)

100-ball BGA (Enhanced)		 Industry-standard packaging enables easier density migration

ClearNAND Webinars

Introduction to ClearNAND
Find out more about the factors driving the need for a solution like ClearNAND technology—why we developed it and what it is—and learn about the product family features, device architecture, and target applications. Our NAND Segment Marketing Manager Cecilia Regolo delivers this informative overview.

Enhanced ClearNAND Flash for Enterprise Applications
Take a deeper dive into the functionality and features of our advanced Enhanced ClearNAND Flash for enterprise applications. Senior Technical Marketing Manager Jim Cooke presents a detailed explanation of the key features that enable better, more efficient designs, including volume select, electronic DQ mirroring, interrupt function, and internal copyback.

Type Secure Title & Description ID# Updated Size
NAND Flash Performance Increase :  Customers using the PAGE READ CACHE MODE operation provided in Micron NAND Flash devices will realize significant performance gains in systems requiring increased data volume at a much faster rate. TN-29-01 05/2007 205.94 KB
Small Block vs. Large Block NAND Devices:  Large-block NAND Flash devices offer significant performance increases over their small-block NAND Flash counterparts for READ, PROGRAM, and ERASE operations. TN-29-07 05/2007 387.87 KB
NAND Flash Security:  Using Micron NAND Flash security features to implement component and code authentication security solutions, designers can protect critical system components and proprietary system software from unwanted attacks and alterations. TN-29-11 05/2007 189.32 KB
Monitoring Ready/Busy Status in 2, 4, and 8Gb Micron NAND Flash Devices:  Four options for determining the NAND Flash ready/busy device status are presented with detailed explanations of each option. TN-29-13 05/2007 96.08 KB
NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command:  This technical note discusses the benefits of PROGRAM PAGE CACHE MODE operations over normal PROGRAM PAGE operations. It also provides specific timing examples and instructions for performing PROGRAM PAGE CACHE MODE operations. Rev. C TN-29-14 02/2010 266.14 KB
Boot-from-NAND Using Micron MT28F1G08ABA NAND Flash with the Texas Instruments OMAP 2420 Processor:  Describes Boot-from-NAND using Micron MT29F1G08ABA NAND Flash with the Texas Instruments OMAP 2420 processor. TN-29-16 06/2007 435.55 KB
Booting from Embedded MMC:  Describes booting from an embedded ARM processor in the MMC environment TN-29-18 06/2008 282.02 KB
NAND Flash 101 - An Introduction to NAND Flash and How to Design It In to Your Next Product:  Provides an introduction to NAND Flash and how to design it into your next product. Rev. B TN-29-19 04/2010 968.5 KB
Improving NAND Flash Performance Using Two-Plane Command Enabled Micron Devices:  Describes the performance benefits of Micron two-plane commands, and provides implementation guidelines for making the best use of two-plane capabilities TN-29-25 09/2008 123.28 KB
NAND Flash Status Register Response in Cache Programming Operations:  Describes status register responses when operating in cache programming modes TN-29-26 06/2007 253.71 KB
Memory Management in NAND Flash Arrays:  Describes common NAND Flash memory-management methods for effective use of the NAND Flash memory array TN-29-28 12/2009 271.42 KB
Using COPYBACK Operations to Maintain Data Integrity in NAND Flash Devices:  Describes how to use COPYBACK operations in NAND Flash devices TN-29-41 10/2008 101.39 KB
Wear-Leveling Techniques in NAND Flash Devices:  Highlights the importance of wear leveling, explains two wear-leveling techniques, and discusses implementing wear leveling TN-29-42 10/2008 268.3 KB
NAND Flash Performance Improvement Using Internal Data Move:  NAND data management capabilities and higher system performance through NAND Flash internal data moves TN-29-15 03/2010 219.17 KB
IBIS Behavioral Models:  Micron has been a member of the IBIS Open Forum for many years and fully supports the IBIS specification. IBIS models for most Micron products are available for download from the Micron Web site. TN-00-07 11/2009 163.98 KB
Thermal Applications:  Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature TN-00-08 05/2010 252.18 KB
Understanding Quality and Reliability Requirements for Bare Die Applications:  Describes the quality and reliability requirements for bare die applications TN-00-14 10/2009 152.83 KB
Recommended Soldering Parameters:  Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 03/2007 69.09 KB
Uprating of Semiconductors for High-Temperature Applications:  Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 428.33 KB
Understanding Signal Integrity:  Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 1.52 MB
SEMI Wafer Map Format:  Micron has adopted the wafer map file format approved by Semiconductor Equipment and Materials International (SEMI). With SEMI formatting, Micron's customers can be confident they will always receive consistent, compatible, reliable map files. TN-00-21 02/2009 110 KB
Thinning Considerations for Wafer Products:  Information on optimal wafer-thinning processes to meet specific customer requirements TN-00-19 10/2009 73.58 KB
Next-Generation NAND Flash Part Numbering System:  Part numbering guide for Micron Next-Generation NAND Flash products. 08/2009 35.73 KB
Small Page SLC (128Mb - 1Gb):  NAND Flash Software driver 11/2009 9.59 KB
Standard NAND Flash Part Numbering System:  Part numbering guide for Micron Standard NAND Flash products. 02/2009 28.52 KB
Flash Memory Technology Direction:  This paper explains the trade-offs associated with available disk caching methods, the differences between various types of Flash memory, and the advantages that NAND offers when superior performance is critically important. 12/2009 643.16 KB
PCN/EOL Systems:  Explains Micron's product change notification and end-of-life systems. CSN-12 08/2009 75.58 KB
Wafer Packaging and Packaging Materials:  Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 09/2011 776.24 KB
Bare Die SiPs and MCMs:  Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 151.06 KB
Shipping Quantities:  Provides tables of part quantity. CSN-04 10/2011 463.55 KB
Micron Component and Module Packaging:  Explanation of Micron packaging labels and procedures. CSN-16 02/2012 840.61 KB
ESD Precautions for Die/Wafer Handling and Assembly:  Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 119.08 KB
Electronic Data Interchange:  Describes EDI transmission sets, protocol, and contacts. CSN-06 09/2005 53.5 KB
RMA Procedures for Packaged Product and Bare Die Devices:  Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 10/2010 82.64 KB
ISO System Management Standards:  Describes ISO system management standards. CSN-08 04/2004 39.18 KB
ONFI Standards and What They Mean to Designers:  Inconsistencies without ONFI and results with ONFI 12/2009 166.18 KB
Optimizing NAND Flash Performance:  Improving NAND performance in various applications 12/2009 149.28 KB
A Closer Look at NAND Flash:  Exploring the possibilities of SSDs 12/2009 2.7 MB
The Inconvenient Truths of NAND Flash Memory:  Overview of NAND Flash 12/2009 344.36 KB
Overcoming (or Embracing) the Dreaded Single-Source Dilemma:  Multisourcing versus single-sourcing 12/2009 241.11 KB
NAND Flash Reliability and Performance - The Software Effect:  NAND software 12/2009 296.15 KB
Introduction to Flash Memory:  Basics of Flash memory 12/2009 1.11 MB
Power Requirements for Multi-Bit Per Cell NAND Flash:  Technology differences, power consumption considerations 12/2009 90.65 KB
3-Bit/Cell NAND Flash:  Architecture, performance, endurance, system requirements, cost advantages, applications 12/2009 90.87 KB
NAND Flash Consideratons for Consumer Applications:  NAND requirements/system reliability in consumer applications 12/2009 700.54 KB
Improving Power Budgeting Estimates in NAND Applications:  Measuring Icc with better predictability 12/2009 694.29 KB
The Many Flavors of NAND...and More to Come:  Keynote for Flash Memory Summit 2009 12/2009 8.03 MB
NAND Flash Architecture and Specification Trends:  How to prepare for changes brought on by technology shrinks 12/2009 696.58 KB
An ONFI Update:  Overview of enhancements and the path to higher performance 12/2009 1007.42 KB
Choosing the Right NAND for Your Application:  Market overview, traditional versus newer devices, and Micron's broad product offering 12/2009 2.72 MB
Micron® ECC Module for NAND Flash via Xilinx® Spartanâ„¢-3 FPGA:  Micron® ECC module was developed and tested using Xilinx® Spartanâ„¢-3 and can be ported to certain other platforms of the user’s choosing. TN-29-05 05/2007 997.75 KB
Micron® NAND Flash Controller via Xilinx® Spartanâ„¢-3 FPGA:  Describes the Micron NAND Flash controller, techniques for interfacing the NAND Flash device with a processor, and use of the Micron glueless interface to interface a processor with NAND Flash memory. TN-29-06 06/2007 872.4 KB
ONFI 2.0: High Speed NAND Overview:  Discusses the limitations of the NAND interface and how ONFI 2.0 helps overcome performance limitations and provide greater scalability. Presented by Applications Engineering Manager and ONFI Technical Team Member, Michael Abraham. 11/2007 158.84 KB
TN-29-37: Comparing 40 and 50-Series SLC NAND Flash Devices:  Prior to conversion, Micron recommends that the target design take into account the product data sheet and the specific changes highlighted in this technical note. This Technical note covers the M58A, M59A & M50A products. TN-29-37 01/2009 728.87 KB
FBGA Date Codes:  Date codes for FBGA-packaged components 08/2005 22.36 KB
NAND Flash Controller on Spartan-3:  This technical note describes the Micron NAND Flash controller, techniques for interfacing the NAND Flash device with a processor and use of the Micron glueless interface to interface a processor with NAND Flash memory. TN-29-06 06/2007 872.4 KB
ECC Module for Xilinx Spartan-3:  Describes the Micron® ECC module that was developed and tested using Xilinx® Spartanâ„¢-3 and can be ported to certain other platforms of the user’s choosing. TN-29-05 05/2007 997.75 KB
Accelerate Design Cycles with Simulation Models:  Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 206.91 KB
Determining NAND Flash Ready/Busy Status:  Systems that utilize NAND Flash memory can use either the ready/busy pin or the status register to determine whether a Micron® NAND Flash device is busy or ready to accept a new command. This technical note addresses the use of status register bit 5, which indicates the ready/busy status of the NAND Flash device. TN-29-13 02/2010 136.48 KB
1-Bit Software ECC:  NAND Flash software driver ECC 12/2009 3.26 KB
TN-29-51: Migrating from 50-Series to 60-Series SLC NAND Flash Devices:  Migrating from 50-Series to 60-Series SLC NAND Flash Devices; M58A, M59A, M50A, M68A, M69A, M60A TN-29-51 05/2011 121.59 KB
TN-29-52: Migrating 1Gb 48nm and 2Gb/4Gb 57nm SLC NAND Flash Memory to 34nm:  Provides guidelines for migrating 1Gb 48nm and 2Gb/4Gb 57nm SLC, large-page NAND Flash memory to 34nm technology (M60A, M69A & M68A) TN-29-52 10/2010 180.46 KB
TN-29-17: NAND Flash Design and Use Considerations:  Describes design and use considerations for NAND Flash memory, focusing on bad-block identification and error correction. TN-29-17 09/2010 226.04 KB
Migrating from a Chip Enable Care to a Don't Care NAND Flash Memory:  The purpose of this application note is to highlight the differences between Chip Enable don’t care and Chip Enable care devices. AN2365 10/2010 265.78 KB
Micron Wire-Bonding Techniques:  This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 66.13 KB
TN-29-56: Enabling On-Die ECC for OMAP3 on Linux/Android OS:  Enabling NAND On-Die ECC for OMAP3 Using Linux/Android OS with YAFFS2. M60A, M69A, M68A. TN-29-56 12/2010 331.14 KB
Flash + Controller Part Numbering System:  05/2011 27.92 KB
Improving Enterprise System Performance with a New Breed of NAND Flash:  Micron's ClearNAND Flash devices allow for more cost-effective and higher-performance controllers by saving hundreds of signals and potentially millions of logic gates. 01/2011 1.17 MB
TN-29-58: ONFI NV-DDR2 Design Guide:  Rev. A TN-29-58 03/2011 685.04 KB
TN-29-57: Migrating from 50-Series to 60-Series SPI NAND:  Supplements the product change notification (PCN) covering the transition from Micron® 50-series (50nm) to 60-series (34nm) single-level cell (SLC) SPI NAND Flash devices. TN-29-57 05/2011 164.87 KB
How ClearNAND Flash Simplifies and Enhances System Designs:  Discusses NAND Flash trends and complexities; NAND interface choices; and how Micron's Enhanced ClearNAND Flash helps eliminate the impact of NAND's ever-increasing ECC requirements. White Paper 07/2011 814.8 KB
Micron BGA Manufacturer's User Guide:  Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 07/2011 353.32 KB
ONFI Flyer:  06/2009 162.55 KB
System Benefits of EZ-NAND/Enhanced ClearNAND Flash:  08/2011 1.77 MB
FMS2011 Keynote:  08/2011 2.41 MB
Current and Emerging Memory Technology Landscape:  08/2011 2.78 MB
NAND Flash Comparisons for Mobile:  08/2011 4.84 MB
Looking Ahead at Flash Memory:  08/2011 6.43 MB
400 MT/s NAND Interface Solutions:  08/2011 2 MB
Physical NAND Flash Security:  08/2011 2.32 MB
NAND 201: An Update on the Continued Evolution of NAND Flash:  Chronicles the developments in NAND technology from 2006 through early 2011. Article 09/2011 641.28 KB
Large Page SLC (1Gb, 4Gb):  NAND Flash Software driver 01/2010 17.27 KB
Product Marks/Product and Packaging Labels:  Explains product part marking, and product and packaging labels. CSN-11 02/2012 666.83 KB
Data Design Case Study:  01/2012 446.92 KB
Compatibility Guide for Micron Software Device Drivers Available on micron.com:  This document lists the compatible NOR, NAND, and PCM devices for the software device drivers available for download from micron.com. Product Flyer 02/2012 227.69 KB
NAND Flash Low Level Drivers for x16 Devices:  01/2010 15.34 KB
Very Large Page SLC (8Gb):  NAND Flash Software driver 03/2010 10.23 KB
BeagleBoard SPI NAND MTD for Linux 2.6.33:  SPI NAND GPL drivers for 50 series NAND. 06/2011 9.65 KB
Bypass Capacitor Selection for High-Speed Designs:  Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 481.9 KB
Enabling a Flash Memory Device into the Linux MTD:  The technical note introduces the Linux memory technology device (MTD) architecture and provides a basis for understanding how to enable new devices and new features into the Linux MTD. TN-00-25 05/2011 528.81 KB
Hamming Codes for NAND Flash Memories:  Outlines hamming codes NAND Flash memory TN-29-08 05/2007 229.46 KB
Bad Block Management in NAND Flash Memory:  This technical note explains how to recognize factory-generated bad blocks and manage bad blocks that develop during the lifetime of NAND Flash memory. TN-29-59 10/2010 317.81 KB
Garbage Collection in SLC NAND Flash Memory:  This technical note describes the recommended garbage collection algorithm to be implemented in the Flash Translation Layer (FTL) software for single-level cell (SLC) NAND Flash memory devices. AN1821 10/2010 207.37 KB
Wear Leveling in NAND Flash Memory:  This technical note describes the recommended wear leveling algorithm to be implemented in the FTL software for NAND Flash memory. TN-29-61 10/2010 213.59 KB
Software Device Drivers for Large Page Micron NAND Flash Memory Devices:  This technical note explains how to use the Micron large page NAND Flash memory software device drivers. TN-29-62 10/2011 624.45 KB
Error Correction Code in SLC NAND Flash:  This technical note describes how to implement error correction code (ECC) in Micron small page and large page single-level cell (SLC) NAND Flash memory that can detect 2-bit errors and correct 1-bit errors per 256 or 512 bytes. TN-29-63 10/2010 486.67 KB
Software Device Drivers for Small Page Micron NAND Flash Memory:  This technical note explains how to use the Micron small page NAND Flash memory software drivers. TN-29-64 10/2010 889.73 KB
Software Device Drivers for Very Large Page Micron NAND Flash Memory:  This technical note explains how to use the Micron very large page NAND Flash memory software device drivers. TN-29-65 10/2010 405.64 KB

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How do I achieve greater program/read throughput with a ClearNAND device?
You need to operate at the fastest supported timing mode to get the maximum program/read throughput with Micron ClearNAND Flash. For Standard ClearNAND devices, use multiplane operations wherever possible; for Enhanced ClearNAND devices, issue queued commands via the enhanced command set to improve the device throughput. See the ClearNAND device data sheet for details on how to use these commands.
I am seeing a lot of read disturb errors. Can you tell me if there is a problem with your part?
Read disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read disturb errors. However, to mitigate any errors received due to read disturb, we recommend refreshing the data to reduce the amount of times the same data is read.
What types of errors occur with ClearNAND devices compared to traditional NAND?
ClearNAND devices offer additional reliability compared to traditional NAND due to internal ECC, though the same types of errors are present. The host controller can determine whether blocks should be retired or data should be refreshed by monitoring the device status registers following each operation. Additional Micron NAND Flash technical information can be found on the NAND Flash Technical Notes page.
Where can I find simulation models for ClearNAND Flash devices?
Micron posts Verilog, HSpice, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why doesn't the ClearNAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a RESET command (FFh) to the NAND device after powering on the device. A RESET command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.
Will ClearNAND Flash require new types of controllers?
Standard ClearNAND devices can be used with existing controllers if the controllers support the ONFI 2.3 EZ NAND specification. To take full advantage of the capabilities of our Enhanced ClearNAND device, controllers will need to support the latest ONFI industry standard and incorporate the enhanced command sequences detailed in the device data sheet.
How is ClearNAND Flash different from traditional NAND?
ClearNAND devices are comprised of an internal controller packaged with one or more NAND devices in an MCP. The controller handles the NAND’s ECC requirement and offloads ECC from the host controller. Both Standard and Enhanced ClearNAND devices report ECC success/fail to the host controller via status registers. In addition, Enhanced ClearNAND devices offer a new enhanced command set to increase overall device performance by allowing command queuing.
Do you support small block devices?
Currently, Micron only offers large block devices. For more information, please refer to Technical Note, TN-29-07: Small Block vs. Large Block NAND Devices.
How do I achieve greater PROGRAM/READ throughput for the NAND device?
To get the maximum PROGRAM/READ throughput for Micron NAND Flash devices, use the PROGRAM and READ CACHE operations. See the NAND device data sheet and our NAND Technical Notes Page for details on how to use these commands.
How is Nvb specified?
Nvb is specified as the minimum number of valid blocks at the end of the P/E cycle spec.
How much ECC do I need to support your devices?
We define our ECC requirement per 512-byte section. MLC NAND devices have a higher ECC requirement than SLC NAND due to the increased number of bits per cell. ECC requirements differ for designs, so consult the device data sheet for the amount of ECC needed.
I am seeing a lot of READ DISTURB errors. Can you tell me if there is a problem with your part?
READ disturb occurs when the same data is read repeatedly. By its nature, NAND technology has a very low occurrence of read-disturb errors. But, to mitigate any errors received due to read disturb, we recommend that users refresh the data to reduce the amount of times the same data is read.
I am using the correct amount of error correction code (ECC) for the NAND device, but I’m still seeing bit/byte errors in data I read back from the NAND device.
Make sure that you are issuing a READ STATUS command to the NAND device after any type of PROGRAM or ERASE operation. Checking status after a PROGRAM or ERASE operation will report whether the PROGRAM or ERASE operation was successful. If the READ STATUS command reports a failure with a PROGRAM operation, that data should be programmed somewhere else and the block being programmed should be retired. If the READ STATUS command reports a failure with an ERASE operation, that block should also be retired.
I’ve heard that NAND has too many errors to boot from. Is this true?
With ECC, NAND can achieve bit error rates (BER) that are comparable with NOR, which is commonly used as a booting device. Applications that use NAND typically copy the booting code to DRAM and execute from DRAM. For more information, read Tech Note 29-16, which is geared to a specific processor, but the concepts can be applied generally. TN-29-19 is a very useful technical note on the general concepts of NAND.
Should I be marking blocks bad due to READ errors?
Yes.
What NAND parts have been validated with the OMAP35x?
Micron works closely with Texas Instruments (TI) to validate and optimize our parts for the OMAP35x processors. As we work with the OMAP35x team, the list of validated memory devices expands frequently. For the most current information, contact your local Micron support.
When I issue a Read ID command (90h) to a two-die NAND device, I get a device ID back that states it is a one-die NAND device.
In a two-die NAND device, where a single die is on each CE#, the device ID that is returned is per CE# for one die. For example, an 8Gb two-die NAND device with two CE# pins would return a 4Gb device ID on each CE#. See the Read ID section of the NAND device data sheet for more details.
Where can I find additional technical information about Micron NAND devices that is not covered in the device data sheets?
Additional Micron NAND Flash technical information—including details on performance enhancing commands—can be found on the Technical Notes page for NAND.
Where can I find simulation models for NAND Flash devices?
Micron posts Verilog, HSPICE, and IBIS models for NAND devices. To find the right model for your needs, see the appropriate NAND part catalog and select your device to view the available models.
Why am I getting a bit/byte error reading back the information I programmed into the NAND device?
Check that you are using the appropriate amount of error correction code (ECC) for the NAND device. The ECC threshold can be found in the "Error Management" section of the NAND device data sheet. Also ensure that none of the bad blocks marked by the NAND manufacturer (Micron) are used. See the "Error Management" section of the NAND device data sheet for more details on how to search for manufacturer-marked bad blocks.
Why doesn't the NAND Flash device respond correctly to commands issued to it?
Be sure you are issuing a reset command (FFh) to the NAND device after powering on the device. A reset command (FFh) must be issued to each valid chip enable (CE#) of the NAND device before any commands are allowed to be issued to that CE#.

ClearNAND

Related Information

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