FBDIMM

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Unleashing Server Capacity

Engineered for servers, our FBDIMMs increase speed, capacity, and reliability.

blue serversManaging the Challenges of Server Speed and Density

Speed and Scalability
Our FBDIMM technology solves server challenges for you—and for your customers. Our high-speed, high-density FBDIMMs can give you virtually unlimited scalability of density and high-bandwidth solutions, all with an extremely reliable channel protocol.

How do we do it? At the core of FBDIMM architecture is an advanced memory buffer (AMB), which provides an interface from the DRAM through the high-speed information channel. Our FBDIMM technology uses DDR2 memory with a different topology, and this high-speed, point-to-point interface rapidly transmits signals among the controller, memory devices, and other modules, enabling simultaneous task performance (and eliminating additional dead time), while reducing soft errors.

With data rates as high as 4.8 Gb/s, our FBDIMMs enable extremely fast buffering—optimizing server performance, limiting data inaccuracies, avoiding crashes, and improving overall reliability. These modules are available in 512MB to 8GB configurations and can be scaled to meet almost any server challenge.

FBDIMM Part Catalogs and Documentation

Advanced Memory Buffer
The AMB maintains signal integrity and improves error detection methods, reducing soft errors. This simplified structure gives FBDIMMs a lower pin count and faster transmission rates than conventional architectures. Plus, they can perform reads and writes simultaneously, eliminating the read-to-read delay between data transfers. With speeds up to 4.8 Gb/s, our FBDIMMs enable fast buffering to optimize server performance.

Improved Error Detection
Our FBDIMMs incorporate an enhanced cyclic redundancy check (CRC) that provides greater data and address/command protection than traditional server modules. You can also configure the CRC to suit your application.

Other Key Benefits

Extended Memory Capacity
High-density solutions for extended memory capacity.

Reliability and Compatibility
We use stringent quality and reliability tests and work with chipset vendors to validate our modules to ensure you get high-quality parts.

Extended Temperature Range
An extended temperature range provides optimum performance and proven reliability in rugged environments.

    Features Benefits
    Densities 512MB to 8GB Wide range of densities supports moderate to high-density applications; eliminates memory capacity limits
    Configuration x72 Various ECC algorithms supported with FBDIMM protocol; improved error detection dramatically reduces soft errors
    Supply Voltages 1.55
    1.8V    		 Multiple voltages enable flexibility for designs
    Clock Frequencies PC2-5300 to PC2-6400 Supports DRAM data rates of 667 and 800 MT/s
    Temperature Ranges 0°C to +95°C Increased operating range for optimum functionality in extreme environments
    Special Features Advanced memory buffer (AMB) Buffers all signals to and from DRAM, which increases system capacity; provides high-speed serial interface between memory controller and AMB; uses traditional DRAM interface between AMB and conventional DRAM; newly advanced channel features vastly improve performance

    Type Secure Title & Description ID# Updated Size
    Thermal Applications:  Defines a general method and criteria for measuring and ensuring that Micron components and modules do not exceed the maximum allowable temperature TN-00-08 05/2010 252.18 KB
    Recommended Soldering Parameters:  Defines the recommended soldering techniques and parameters for Micron Technology, Inc., products. TN-00-15 03/2007 69.09 KB
    Uprating of Semiconductors for High-Temperature Applications:  Describes the issues associated with temperature uprating and the risks involved in using components and/or systems outside the manufacturer's environmental specifications TN-00-18 05/2010 428.33 KB
    Understanding Signal Integrity:  Describes how memory design, test, and verification tools can be used to the greatest advantage, from conception of a new product through end of life TN-00-20 12/2009 1.52 MB
    Memory Module Serial Presence-Detect:  Describes how SPD is essential in helping to standardize the configuration, timing, and manufacturing information of memory modules TN-04-42 12/2009 505.83 KB
    Comparing Module Parameters:  Compares module parameters. TN-04-49 03/2003 52.71 KB
    High-Speed DRAM Controller Design:  Identifies and discusses five key areas of DRAM controller design TN-04-54 04/2008 1 MB
    DRAM Module Form Factors:  Compares the most common DRAM module form factors TN-04-55 09/2009 435.56 KB
    FBDIMM Channel Utilization (Bandwidth and Power):  Newly introduced FBDIMMs offer virtually unlimited scalability of density, a significantly reduced number of routed motherboard signals, and high bandwidth solutions, all with an extremely reliable channel protocol TN-47-21 12/2009 1.21 MB
    Designing for 1.5V, Low-Power FBDIMMs:  Discusses memory power trends and identifies new low-voltage solutions for high-density DDR2 memory designs TN-47-22 05/2008 980.89 KB
    Module Part Numbering Systems:  Part numbering guides for Micron DDR3, DDR, DDR, and SDRAM modules. 02/2012 41.77 KB
    Driving Down Power Consumption in Data Centers:  A success story about how Egenera increased the energy efficiency of its data center virtualization systems by designing in Micron's low-voltage memory. 12/2009 219.05 KB
    Server Memory Solutions for the Impending Data Center Power Crisis:  Facts about data center energy consumption and information about how to achieve significant power savings with Micron's low-voltage memory modules for servers. White Paper 12/2009 309.03 KB
    PCN/EOL Systems:  Explains Micron's product change notification and end-of-life systems. CSN-12 08/2009 75.58 KB
    Wafer Packaging and Packaging Materials:  Provides complete shipping and recycling information about each of the materials used for shipping Micron's products. CSN-20 09/2011 776.24 KB
    Bare Die SiPs and MCMs:  Describes design considerations for bare die SiPs and MCMs. CSN-18 04/2009 151.06 KB
    Shipping Quantities:  Provides tables of part quantity. CSN-04 10/2011 463.55 KB
    Micron Component and Module Packaging:  Explanation of Micron packaging labels and procedures. CSN-16 02/2012 840.61 KB
    ESD Precautions for Die/Wafer Handling and Assembly:  Describes the benefits of controlling ESD in the workplace, including higher yields and improved quality and reliability, resulting in reduced manufacturing costs. CSN-24 08/2010 119.08 KB
    Electronic Data Interchange:  Describes EDI transmission sets, protocol, and contacts. CSN-06 09/2005 53.5 KB
    RMA Procedures for Packaged Product and Bare Die Devices:  Outlines standard returned material authorization (RMA) procedures, as well as the differences associated with bare die RMAs. CSN-07 10/2010 82.64 KB
    ISO System Management Standards:  Describes ISO system management standards. CSN-08 04/2004 39.18 KB
    Competitive DDR Memory Subsystems:  DDR milestones and platform design 12/2009 2.64 MB
    DDR System Design Considerations:  DDR overview 12/2009 3.46 MB
    The Future of Memory and Storage:  Overview of trends for main memory and Flash memory 12/2009 1.54 MB
    Design Guide for Two DDR3-1066 UDIMM Systems:  Rev. B, Design guide to assist board designers implementing products using UDIMM systems TN-41-08 01/2010 1.1 MB
    Moisture Absorption in Plastic Packages:  Describes shipping procedures for preventing memory devices from absorbing moisture and recommendations for baking devices exposed to excessive moisture TN-00-01 02/2010 87.26 KB
    Accelerate Design Cycles with Simulation Models:  Micron supplies the tools and guidelines necessary to verify new designs prior to layout. This technical note discusses software model support, signal integrity optimization, and logic circuit design. TN-00-09 02/2010 206.91 KB
    Micron Wire-Bonding Techniques:  This technical note provides guidance on wire bonding techniques for both nickel-palladium (NiPd) and aluminum (Al) bond pads on Micron products. TN-00-22 11/2010 66.13 KB
    Fully Buffered DIMM Flyer:  Describes how FBDIMMs unleash server capacity by removing the density/performance tradeoff of traditional stub-bus architectures 12/2007 146.44 KB
    Micron BGA Manufacturer's User Guide:  Provides information to enable customers to easily integrate both leading-edge and legacy Micron's ball grid array (BGA) packages into their manufacturing processes. It is intended as a set of high-level guidelines and a reference manual describing typical package-related and manufacturing process-flow practices. CSN-33 07/2011 353.32 KB
    Proper Handling Procedures for Micron DIMMs:  12/2009 396.18 KB
    Proper Installation Procedures for Micron DIMMs:  12/2009 419.89 KB
    Proper Handling of Micron DIMMs - Japanese:  12/2009 453.96 KB
    Proper Installation of Micron DIMMs - Japanese:  12/2009 394.2 KB
    Proper Handling of Micron DIMMs - Simplified Chinese:  12/2009 482.47 KB
    Proper Installation of Micron DIMMs - Simplified Chinese:  12/2009 592.58 KB
    Proper Handling of Micron DIMMs - Spanish:  12/2009 461.82 KB
    Proper Installation of Micron DIMMs - Spanish:  12/2009 546.81 KB
    Proper Handling of Micron DIMMs - Traditional Chinese:  12/2009 539.92 KB
    Proper Installation of Micron DIMMs - Traditional Chinese:  12/2009 758.93 KB
    Product Marks/Product and Packaging Labels:  Explains product part marking, and product and packaging labels. CSN-11 02/2012 666.83 KB
    Bypass Capacitor Selection for High-Speed Designs:  Describes bypass capacitor selection for high-speed designs. TN-00-06 03/2011 481.9 KB

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    Can Vtt and Vref be supplied by the same supply in my system design?
    With proper decoupling this can be an acceptable design. However, Micron recommends ensuring all supplies are separated. Vref tends to have more noise on it because it supplies signals that are regularly switching. A robust design would typically not connect these supplies due to the possibility of introducing this noise onto the Vtt plane which should be as stable as possible. Additionally, Vref requires much less current than Vtt.
    Is there a set of trace lengths and routing rules that are standard for use when designing a system that uses a specific module technology and form factor?
    No. A robust memory subsystem design that includes the use of 1 or more memory modules must be simulated in order to determine the optimum trace lengths, terminations. However, our design guides such as TN-47-01 and TN-41-08 have some best practices and design examples based on some typical system assumptions. This information is not meant to be the only way your system can be designed. It is a starting point and moreover an example of the steps used to determine the best design for your system.

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